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| Small Outline, 5 Lead, High CMR, High Speed, Logic Gate Optocouplers Technical Data HCPL-M600 HCPL-M601 HCPL-M611 Features * Surface Mountable * Very Small, Low Profile JEDEC Registered Package Outline * Compatible with Infrared Vapor Phase Reflow and Wave Soldering Processes * Internal Shield for High Common Mode Rejection (CMR) HCPL-M601: 10,000 V/s at VCM = 50 V HCPL-M611: 15,000 V/s at VCM = 1000 V * High Speed: 10 Mbd * LSTTL/TTL Compatible * Low Input Current Capability: 5 mA * Guaranteed ac and dc Performance over Temperature: -40C to 85C * Recognized under the Component Program of U.L. (File No. E55361) for Dielectric Withstand Proof Test Voltage of 2500 Vac, 1 Minute Description These small outline high CMR, high speed, logic gate optocouplers are single channel devices in a five lead miniature footprint. They are electrically equivalent to the following Agilent optocouplers (except there is no output enable feature): SO-5 Package HCPL-M600 HCPL-M601 HCPL-M611 Standard DIP 6N137 HCPL-2601 HCPL-2611 SO-8 Package HCPL-0600 HCPL-0601 HCPL-0611 The SO-5 JEDEC registered (MO155) package outline does not require "through holes" in a PCB. This package occupies approximately one fourth the footprint area of the standard dual-in-line package. The lead profile is designed to be compatible with standard surface mount processes. The HCPL-M600/01/11 optically coupled gates combine a GaAsP light emitting diode and an integrated high gain photon detector. The output of the detector I.C. is an Open-collector Schottky-clamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of 5,000 V/s for the HCPL-M601, and 10,000 V/s for the HCPLM611. This unique design provides maximum ac and dc circuit isolation while achieving TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from -40C to 85C allowing trouble free system performance. CAUTION: The small device geometries inherent to the design of this bipolar component increase the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 2 The HCPL-M600/01/11 are suitable for high speed logic interfacing, input/output buffering, as line receivers in environments that conventional line receivers cannot tolerate, and are recommended for use in extremely high ground or induced noise environments. Applications * Isolated Line Receiver * Simplex/Multiplex Data Transmission * Computer-Peripheral Interface * Microprocessor System Interface * Digital Isolation for A/D, D/A Conversion * Switching Power Supply * Instrument Input/Output Isolation * Ground Loop Elimination * Pulse Transformer Replacement Outline Drawing (JEDEC MO-155) ANODE 1 4.4 0.1 (0.173 0.004) 6 VCC MXXX XXX 7.0 0.2 (0.276 0.008) CATHODE 3 5 VOUT 4 GND 0.4 0.05 (0.016 0.002) 3.6 0.1* (0.142 0.004) 0.102 0.102 (0.004 0.004) 0.15 0.025 (0.006 0.001) 7 MAX. 1.27 BSG (0.050) 0.71 MIN. (0.028) MAX. LEAD COPLANARITY = 0.102 (0.004) DIMENSIONS IN MILLIMETERS (INCHES) * MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006) "Agilent" IS MARKED ON THE UNDERSIDE OF THE PACKAGE 2.5 0.1 (0.098 0.004) Pin Location (for reference only) 4.4 (0.17) 0.3 (0.01) Schematic + 1 IO 5 IF ICC 6 VCC VO 2.5 (0.10) 1.3 (0.05) - 3 HCPL-M601/11 SHIELD 4 GND 0.9 (0.04) 7.2 (0.28) 0.5 (0.02) USE OF A 0.1 F BYPASS CAPACITOR MUST BE CONNECTED BETWEEN PINS 6 AND 4 (SEE NOTE 1). TRUTH TABLE (POSITIVE LOGIC) OUTPUT LED L ON H OFF 3 Recommended Operating Conditions Parameter Input Current, Low Level Input Current, High Level Supply Voltage, Output Fan Out (RL = 1 k) Output Pull-Up Resistor Operating Temperature Symbol IFL* IFH V CC N RL T A 330 -40 Min. 0 5 4.5 Max. 250 15 5.5 5 4,000 85 Units A mA V TTL Loads C * The off condition can also be guaranteed by ensuring that VF(off) 0.8 volts. Absolute Maximum Ratings (No Derating Required up to 85C) Storage Temperature .................................................... -55C to +125C Operating Temperature .................................................. -40C to +85C Forward Input Current - IF (see Note 2) ....................................... 20 mA Reverse Input Voltage - VR ................................................................. 5 V Supply Voltage - VCC (1 Minute Maximum) ........................................ 7 V Output Collector Current - IO ........................................................ 50 mA Output Collector Power Dissipation ............................................ 85 mW Output Collector Voltage - VO ............................................................ 7 V (Selection for higher output voltages up to 20 V is available) Infrared and Vapor Phase Reflow Temperature ....................... see below 260 240 220 200 180 160 140 120 100 80 60 40 20 0 0 T = 145C, 1C/SEC T = 115C, 0.3C/SEC TEMPERATURE - C T = 100C, 1.5C/SEC 1 2 3 4 5 6 7 8 9 10 11 12 TIME - MINUTES Maximum Solder Reflow Thermal Profile. (Note: Use of Non-Chlorine Activated Fluxes is Recommended.) 4 Insulation Related Specifications Parameter Min. External Air Gap (Clearance) Min. External Tracking Path (Creepage) Min. Internal Plastic Gap (Clearance) Tracking Resistance Isolation Group (per DIN VDE 0109) CTI Symbol L(IO1) L(IO2) Value 5 5 0.08 175 IIIa Units mm mm mm V Conditions Measured from input terminals to output terminals Measured from input terminals to output terminals Through insulation distance conductor to conductor DIN IEC 112/VDE 0303 Part 1 Material Group DIN VDE 0109 Electrical Specifications Over recommended temperature (TA = -40C to 85C) unless otherwise specified. (See note 1.) Parameter Input Threshold Current High Level Output Current Low Level Output Voltage High Level Supply Current Low Level Supply Current Input Forward Voltage Input Reverse Breakdown Voltage Input Capacitance Input Diode Temperature Coefficient Input-Output Insulation Resistance (Input-Output) Capacitance (Input-Output) Symbol Min. Typ.* Max. Units ITH IOH VOL ICCH ICCL VF 1.4 1.5 1.3 BVR CIN VF /TA 5 60 -1.6 pF mV/C 1.85 IF = 10 mA IR = 10 A VF = 0V, f = 1 MHz IF = 10 mA 12 2 5.5 0.4 4 6 5 100 0.6 7.5 10.5 1.75 V mA A V mA Test Conditions VCC = 5.5 V, IO 13 mA, VO = 0.6 V VCC = 5.5 V, VO = 5.5 V IF = 250 A VCC = 5.5 V, IF = 5 mA, IOL (Sinking) = 13 mA VCC = 5.5 V, IF = 0 mA, VCC = 5.5 V, IF = 10 mA, TA = 25C 3 Fig. 13 1 2, 4, 5, 13 Note VISO RI-O CI-O 2500 1012 0.6 VRMS pF RH 50%, t = 1 min. VI-O = 500 V f = 1 MHz 3, 4 3 3 *All typicals at TA = 25C, VCC = 5 V. 5 Switching Specifications Over recommended temperature (TA = -40C to 85C), VCC = 5 V, IF = 7.5 mA unless otherwise specified. Parameter Propagation Delay Time to High Output Level Propagation Delay Time to Low Output Level Propagation Delay Skew Symbol tPLH Device HCPL- Min. Typ.* Max. Unit 20 48 75 100 tPHL 25 50 75 100 tPSK 3.5 24 10 tfall 10 10 |CM H| M600 M601 10,000 5,000 10,000 V/s VCM = 10 V VO(min) = 2 V RL = 350 VCM = 50 V IF = 0 mA VCM = 1000 V TA = 25C 11 7, 9 40 35 CL = 15 pF 9 TA = 25C RL = 350 ns Test Conditions TA = 25C Fig. Note 6, 7 8 6, 7 8 10, 11 10 6 5 Pulse Width |tPHL - tPLH| Distortion Output Rise Time (10%-90%) Output Fall Time (10%-90%) Common Mode Transient Immunity at High Output Level Common Mode Transient Immunity at Low Output Level trise M611 10,000 15,000 |CM H| M600 M601 10,000 5,000 10,000 M611 10,000 15,000 VO(max) = 0.8 V 11 RL = 350 VCM = 50 V IF = 7.5 mA VCM = 1000 V T A = 25C VCM = 10 V 8, 9 *All typicals at TA = 25C, VCC = 5 V. Notes: 1. Bypassing of the power supply line is required with a 0.1 F ceramic disc capacitor adjacent to each optocoupler. The total lead length between both ends of the capacitor and the isolator pins should not exceed 10 mm. 2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20 mA. 3. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together. 4. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 3000 VRMS for 1 second (Leakage detection current limit, II-O 5 A). 5. The tPLH propagation delay is measured from 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the output pulse. 6. The tPHL propagation delay is measured from 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the output pulse. 7. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., VOUT > 2.0 V). 8. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VOUT > 0.8 V). 9. For sinusoidal voltages, (|dVCM|/dt)max = fCMVCM(p-p). 10. See application section; "Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew" for more information. 11. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the worst case operating condition range. 6 IOH - HIGH LEVEL OUTPUT CURRENT - A 15 VCC = 5.5 V VO = 5.5 V IF = 250 A 10 VOL - LOW LEVEL OUTPUT VOLTAGE - V 0.5 IF - FORWARD CURRENT - mA VCC = 5.5 V IF = 5.0 mA 100 TA = 25C 10 1.0 IF + VF - 0.4 IO = 12.8 mA 0.3 IO = 16 mA 0.1 5 0.2 IO = 9.6 mA 0.1 -60 -40 -20 IO = 6.4 mA 0.01 0.001 1.10 0 -60 -40 -20 0 20 40 60 80 100 0 20 40 60 80 100 1.20 1.30 1.40 1.50 1.60 TA - TEMPERATURE - C TA - TEMPERATURE - C VF - FORWARD VOLTAGE - VOLTS Figure 1. High Level Output Current vs. Temperature. Figure 2. Low Level Output Voltage vs. Temperature. Figure 3. Input Diode Forward Characteristic. 6 VO - OUTPUT VOLTAGE - V 5 4 3 VCC = 5 V TA = 25 C RL = 350 RL = 1 K PULSE GEN. ZO = 50 tf = tr = 5 ns IF 1 VCC 6 0.1F BYPASS 5 INPUT MONITORING NODE RM *CL 3 GND 4 2 RL = 4 K 1 0 +5 V RL OUTPUT VO MONITORING NODE 0 1 2 3 4 5 6 IF - FORWARD INPUT CURRENT - mA Figure 4. Output Voltage vs. Forward Input current. *CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. IOL - LOW LEVEL OUTPUT CURRENT - mA 80 VCC = 5.0 V VOL = 0.6 V 60 IF = 10 mA, 15 mA 40 IF = 5.0 mA 20 OUTPUT VO IF = 7.5 mA INPUT IF tPHL tPLH IF = 3.75 mA 1.5 V Figure 6. Test Circuit for tPHL and t PLH. 0 -60 -40 -20 0 20 40 60 80 100 TA - TEMPERATURE - C Figure 5. Low Level Output Current vs. Temperature. 7 100 tP - PROPAGATION DELAY - ns tP - PROPAGATION DELAY - ns VCC = 5.0 V IF = 7.5 mA tPLH , RL = 4 K 105 PWD - PULSE WIDTH DISTORTION - ns VCC = 5.0 V TA = 25C tPLH , RL = 4 K 40 RL = 4 k 30 VCC = 5.0 V IF = 7.5 mA 20 RL = 350 k 80 tPHL , RL = 350 1 K 60 4 K 40 90 75 tPLH , RL = 350 tPLH , RL = 1 K tPHL , RL = 350 1 K 4 K 5 7 9 11 13 15 tPLH , RL = 1 K tPLH , RL = 350 60 10 20 45 30 0 RL = 1 k -10 -60 -40 -20 0 20 40 60 80 100 0 -60 -40 -20 0 20 40 60 80 100 TA - TEMPERATURE - C IF - PULSE INPUT CURRENT - mA TA - TEMPERATURE - C Figure 7. Propagation Delay vs. Temperature. Figure 8. Propagation Delay vs. Pulse Input Current. Figure 9. Pulse Width Distortion vs. Temperature. tr, tf - RISE, FALL TIME - ns VCC = 5.0 V IF = 7.5 mA tRISE tFALL IF B +5 V 1 A VCC 6 5 3 4 0.1 F BYPASS 350 OUTPUT VO MONITORING NODE 300 290 60 RL = 4 k RL = 1 k 40 20 0 -60 -40 -20 RL = 350 RL = 350 , 1 k, 4 k 0 20 40 60 80 100 VFF GND TA - TEMPERATURE - C _ + PULSE GENERATOR ZO = 50 VCM (PEAK) 0V VO 5V SWITCH AT A: IF = 0 mA VO (MIN.) SWITCH AT B: IF = 7.5 mA VO (MAX.) CML CMH Figure 10. Rise and Fall Time vs. Temperature. VCM dVF/dT - FORWARD VOLTAGE TEMPERATURE COEFFICIENT - mV/C -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 0.1 VO 0.5 V Figure 11. Test Circuit for Common Mode Transient Immunity and Typical Waveforms. 1 10 100 IF - PULSE INPUT CURRENT - mA Figure 12. Temperature Coefficient for Forward Voltage vs. Input Current. 8 Propagation Delay, PulseWidth Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 7). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 15, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 11 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 16 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The tPSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulse-width distortion and propagation delay skew over the recommended temperature, and input current, and power supply ranges. 9 ITH - INPUT THRESHOLD CURRENT - mA 6 5 4 3 2 VCC = 5.0 V VO = 0.6 V VCC1 5V 470 IF 1 6 390 5 5V VCC 2 RL = 350 RL = 1 k *D1 VF GND 1 3 SHIELD 1 * DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT. 2 4 0.1 F BYPASS GND 2 1 RL = 4 k 0 20 40 60 80 100 0 -60 -40 -20 TA - TEMPERATURE - C Figure 13. Input Threshold Current vs. Temperature. Figure 14. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit. DATA IF 50% INPUTS CLOCK VO 1.5 V IF 50% DATA OUTPUTS tPSK VO 1.5 V tPSK CLOCK tPSK Figure 15. Illustration of Propagation Delay Skew - tPSK. Figure 16. Parallel Data Transmission Example. www.semiconductor.agilent.com Data subject to change. Copyright (c) 1999 Agilent Technologies Obsoletes 5091-9635E (10/93) 5966-4942E (11/99) |
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